1. Field of the Invention
The present invention relates to package substrates, and more particularly, to a coreless package substrate and a fabrication method of the coreless package substrate.
2. Description of Related Art
Electronic devices are made having more functions and higher performance in response to the development of electronic industry. For semiconductor package structures, various types of packages such as a wire-bonded package and a flip-chip package have been developed. With a semiconductor chip being mounted on a package substrate, the wire-bonded package uses bonding wires for electrically connecting the semiconductor chip to the package substrate, whereas in the flip-chip package, the semiconductor chip is electrically connected to the package substrate by solder bumps. Further, considering the high integration and miniaturization requirements for the semiconductor package to accommodate more active and passive components and circuits, the package substrate has been evolved from a double-layer board to a multi-layer board. The multi-layer board involves the use of interlayer connection technique within a limited space in order to provide an increased circuit layout area on the package substrate. This arrangement is suitably used for integrated circuits having high circuit density, reduces thickness of the package substrate, and also reduces the package profile and enhances the electrical performance thereof.
Conventionally the package substrate comprises a core board having inner circuits, and circuit buildup structures symmetrically disposed on two sides of the core board. However, the presence of the core board makes overall thickness of the package substrate hard to be reduced, thereby not in favor of profile miniaturization for the electronic devices.
Accordingly, a coreless package substrate has been developed, which shortens circuit length and decreases overall structure thickness, as required for highly integrated and miniaturized electronic devices. As shown in FIG. 1, the coreless package substrate 1 can be fabricated by the steps of: forming a first dielectric layer 10 on a carrier board (not shown), and forming a first circuit layer 11 on the first dielectric layer 10, the first circuit layer 11 having a plurality of first electrical contact pads 110; forming a circuit buildup structure 12 on the first dielectric layer 10 and the first circuit layer 11, wherein the circuit buildup structure 12 comprises at least a second dielectric layer 120 and a second circuit layer 121 formed on the second dielectric layer 120, wherein the second circuit layer 121 comprises a plurality of second electrical contact pads 123 and is electrically connected to the first circuit layer 11 by conductive vias 122; removing the carrier board to expose the first dielectric layer 10; applying solder mask layers 14a, 14b (such as solder resist) respectively on the first dielectric layer 10 and the second dielectric layer 120 and second circuit layer 121; forming a plurality of openings 140a, 140b through the solder mask layers 14a, 14b and the first dielectric layer 10 to respectively expose partial top surfaces of the first and second electrical contact pads 110, 123; forming metal bumps 13a, 13b respectively in the openings 140a, 140b and mounting solder balls 15a, 15b to the metal bumps 13a, 13b respectively, so as to allow the upper solder balls 15b to bond solder bumps of a chip (not shown) and allow the lower solder balls 15a to mount a circuit board (not shown) thereto.
However in the conventional package substrate 1, as it is required to form the openings 140a, 140b through the solder mask layers 14a, 14b and perform positional alignment between the solder balls 15a, 15b and the openings 140a, 140b, the fabrication method thereof becomes complicated and difficult.
Moreover, only partial top surfaces of the second electrical contact pads 123, instead of the entire top surfaces thereof, are exposed from the openings 140b of the solder mask layer 14b, such that the metal bumps 13b bonded to the exposed partial top surfaces of the second electrical contact pads 123 have relatively small top surfaces for subsequently mounting a chip thereto, thereby making the bonding strength between the metal bumps 13b and the chip relatively weak and allowing the chip to be easily detached and damaged.
Furthermore, in order to avoid short circuiting between the adjacent upper solder balls 15b and to provide sufficient sizes of the openings 140b of the solder mask layer 14b for allowing the metal bumps 13b to be securely bonded to the solder balls 15b, the adjacent second electrical contact pads 123 must have a sufficient pitch distance therebetween and cannot be further closely arranged, such that the layout density of the second electrical contact pads 123 is hardly increased.
Therefore, how to overcome the above drawbacks of the conventional technology is becoming one of the most popular issues in the art.